Due to their fast switching times and high current densities, fin field effect transistor (FinFET) devices are a desired device architecture. In its basic form, a FinFET device includes a source, a drain, and one or more fin-shaped channels between the source and the drain. A gate electrode over the fin regulates electron flow between the source and the drain.
In the semiconductor industry there is a continuing trend toward manufacturing integrated circuits (ICs) with higher densities. Accordingly, smaller feature sizes, smaller separations between features and more precise feature shapes are required in integrated circuits (ICs) fabricated on small rectangular portions of the wafer, commonly known as dies. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, as well as the surface geometry of various other features (e.g., corners and edges). The scaling-down of integrated circuit dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher cost efficiency in IC fabrication by providing more circuits on a die and/or more die per semiconductor wafer.
The architecture of a FinFET device, additionally, presents fabrication challenges. As device features become increasingly smaller (commensurate with current technology) accurately and consistently contacting the source and drain becomes a problem. Some previous FinFET devices have been on single fins, isolated devices or devices having a greatly relaxed pitch.
Moreover, as FinFET device sizes continue to shrink, parasitic capacitance effects may become noticeable and/or problematic. The overlap regions in which source and drain extension regions (LDD regions) overlap with the gate structure can give rise to “overlap capacitances” since the gate structure includes conductive layer(s) overlying dielectric material over a substrate, with the dielectric material situated between the gate structure and diffused conductive dopants in the substrate. The amount of overlap capacitance depends upon the area or degree of overlap between the gate structure and the diffused dopants. As the size of the gate structure is reduced, overlap capacitance becomes significant to reduced transistor performance.